1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having an IC (Integrated Circuit) with a high breakdown voltage.
2. Description of the Background Art
FIG. 13 is a cross section showing a structure of a semiconductor device having an IC with a high breakdown voltage in the prior art. Referring to FIG. 13, a p-type semiconductor substrate 1 has a main surface, at which field oxide films 10 for element isolation are formed with a predetermined space therebetween. An n.sup.- diffusion region 2 is formed at a predetermined region in the main surface of p-type semiconductor substrate 1. The n.sup.- diffusion region 2 forms a well region. There are formed p-type diffusion regions 5 and 6 at the surface of n.sup.- diffusion region 2 so as to be spaced by a predetermined distance with a channel region therebetween. The p-type diffusion regions 5 and 6 form source/drain regions. On the channel region, a gate electrode 8 made of a polycrystalline silicon film is formed with a gate insulating film therebetween. The p-type diffusion regions 5 and 6 as well as gate electrode 8 form a p-channel MOS transistor. At a portion spaced from this p-channel MOS transistor by field oxide film 10, there are formed a pair of n-type diffusion regions 3 and 4 which are spaced from each other by a predetermined distance to locate a channel region therebetween. On the channel region between n-type diffusion regions 3 and 4, there is formed a gate electrode 9 made of a polycrystalline silicon film with a gate insulating film therebetween. The n-type diffusion regions 3 and 4 as well as gate electrode 9 form an n-channel MOS transistor. A p.sup.+ diffusion region 7 is formed under field oxide film 10 which is located between p-type diffusion region 6 and n-type diffusion region 3.
Field oxide film 10 and gate electrodes 8 and 9 are covered with a passivation film 12 for element protection. Contact holes are formed at regions in passivation film 12 corresponding to n-type diffusion regions 3 and 4 and p-type diffusion regions 5 and 6, respectively. There are formed source/drain electrodes which are connected to n-type diffusion regions 3 and 4 and p-type diffusion regions 5 and 6 through these contact holes, respectively. Aluminum electrodes 11 and 15 are formed at predetermined regions on passivation film 12. Aluminum electrode 15 has a potential substantially equal to that on p-type semiconductor substrate 1. Since an IC with a high breakdown voltage is subjected to a high voltage input, an aluminum electrode such as aluminum electrode 11 which attains a high voltage essentially exists in the IC.
A glass coat film 13b is formed over the source/drain regions, aluminum electrodes 11 and 15, and passivation film 12. A mold resin 14 is formed over glass coat film 13b.
When a high input voltage is applied to aluminum electrode 11, an electric field caused by aluminum electrode 11 is small in a room temperature, and this electric field does not significantly affect the n- and p-channel MOS transistors.
In a high temperature, however, aluminum electrode 11 subjected to a high voltage causes a strong electric field, so that p.sup.+ diffusion region 7 is inverted into the n-type, and a parasitic transistor formed of n.sup.- diffusion region 2 and n-type diffusion region 3 is turned on as shown in FIG. 14. Consequently, a leakage current flows in the circuit formed of n- and p-channel MOS transistors which are elements having low breakdown voltages. FIG. 15 schematically shows an equivalent capacitor model along the electric field shown in FIG. 14. Referring to FIG. 15, C1 indicates a capacitance of glass coat film 13b, Cm indicates a capacitance of the mold resin, C2 indicates a total capacitance of field oxide film 10, passivation film 12 and glass coat film 13b. When a voltage (V) is applied to aluminum electrode 11, the voltage is shared in accordance with the capacities of the respective capacitors. A voltage (V2) applied across p-type semiconductor substrate 1 and mold resin 14 is expressed by the following formula (2): EQU V2=V.multidot.C1/(C1+C2+C1.multidot.C2/Cm) (2)
Referring to formula (2), when Cm is sufficiently small, a relationship of (V2&lt;&lt;V) is established. However, mold resin 14 generally has such a property that polarization occurs due to movement of movable ions contained in the resin when an electric field is applied thereto in a high temperature. This polarization of mold resin 14 increases Cm, and hence raises V2. Raised V2 promotes inversion of p.sup.+ diffusion region 7 into n-type as shown in FIG. 14, so that the parasitic MOS transistor is turned on, and the current leakage becomes more liable to occur. The quantity of electric charges, which are accumulated in C2 when p.sup.+ diffusion region 7 is inverted into the n-type, can be calculated from a field inversion voltage (Vtf) and a capacitance (C) of field oxide film 10 by (Q=C2.multidot.V2=C.multidot.Vtf), and is generally from 1.times.10.sup.1 to 1.times.10.sup.12 cm.sup.-2 !. The quantity of electric charges accumulated in C2 is considerably small when the density of mold resin 14 is taken into consideration, and is sufficiently attainable by polarization of mold resin 14. This means that it is difficult to stabilize V2 by improving mold resin 14 itself.
In theory, movable ions contained in mold resin 14 do not stop moving until the electric field disappears in mold resin 14. Therefore, the current leakage due to polarization of mold resin 14 is extremely likely to occur, when IC contains a pole at a voltage higher than V2 which is applied when p.sup.+ diffusion region 7 is inverted into n-type. In the structure of the conventional semiconductor device containing the IC with a high breakdown voltage, as described above, it is difficult to prevent polarization of mold resin 14 if aluminum electrode 11 subjected to a high voltage exists in the IC.